Freescale Semiconductor /MK82F25615 /OTFAD /CR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as CR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (0)FSVM 0 (0)FLDM 0 (0)RRAE 0 (00)CCTX 0 (0)CRCE 0 (0)CRCI 0 (0)GE

CRCE=0, RRAE=0, CRCI=0, FSVM=0, GE=0, CCTX=00, FLDM=0

Description

Control Register

Fields

FSVM

Force Security Violation Mode

0 (0): No effect on the operating mode.

1 (1): Force entry into SVM after a write with this data bit set and the data bit associated with FLDM cleared. SR[MODE] signals the operating mode.

FLDM

Force Logically Disabled Mode

0 (0): No effect on the operating mode.

1 (1): Force entry into LDM after a write with this data bit set. SR[MODE] signals the operating mode.

RRAE

Restricted Register Access Enable

0 (0): Register access is fully enabled. The OTFAD programming model registers can be accessed “normally”.

1 (1): Register access is restricted and only the CR, SR and CRC can be accessed; others are treated as RAZ/WI.

CCTX

CRC Context

0 (00): Enable CTX0 CRC check.

1 (01): Enable CTX1 CRC check.

2 (10): Enable CTX2 CRC check.

3 (11): Enable CTX3 CRC check.

CRCE

CRC Enable

0 (0): CRC-32 is disabled.

1 (1): CRC-32 for the context defined by CR[CCTRX] is enabled.

CRCI

CRC Initialization

0 (0): CRC data register is unaffected.

1 (1): CRC data register is immediately initialized after a write with this data bit set.

GE

Global OTFAD Enable

0 (0): OTFAD has decryption disabled, and bypasses all data fetched by the QuadSPI.

1 (1): OTFAD has decryption enabled, and processes fetched data as defined by the hardware configuration.

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